The preferred embodiment of the invention is specially adapted to solve an increasing problem in high-speed integrated circuits in which an externally applied clock is intended to be registered with other signals present in the integrated circuit. The external clock is frequently applied to a large number of circuits so that their operation can be synchronized to each other. As a result, the signal path to which the external clock signal is applied is capacitively loaded to a far greater degree than signal paths receiving other signals. As a result of this heavy capacitive loading, the external clock signal may be delayed significantly before it reaches the internal circuits in the integrated circuit. This delay may be so significant that the delayed external clock signal fails to be properly registered with other signals.
The above-described problem is exemplified by the integrated circuit 10 shown in FIG. 1. The integrated circuit 10 may be any of a wide variety of digital circuits including DRAMs, SRAMs, bus bridges, etc. that receives an external clock CLK signal and a data signal D, in addition to a large number of other signals which have been omitted for the purpose of brevity and clarity. The clock signal is coupled through a signal path 12 to a number of circuits 14a, 14b, 14n which use the clock signal for a variety of purposes. Once again, the circuits 14a-n can be any of a variety of circuits conventionally used in integrated circuits. The externally applied clock CLK signal is often used to synchronize the entire operation of the integrated circuit 10 and is thus typically routed to a large number of circuit nodes. As a result, the capacitive loading on the signal path 12 is relatively high. In particular, the capacitive loading on the signal path 12 will often be far higher than the capacitive loading on a data path 20 extending from an external terminal D to a far fewer number of signal nodes or to a single node which, in this example, is a NAND gate 22. As a result, there is relatively little delay of the data signal as it is coupled from the D terminal to the NAND gate 22 compared to the delay of the clock signal as it is coupled to the NAND gate 22 and the other circuits 14a-n. Because of this delay, the clock input to the NAND gate 22 is designated a delayed clock CLK-DEL.
The operation of the exemplary circuit 10 shown in FIG. 1 is best explained with further reference to the timing diagram of FIG. 2. As shown in FIG. 2, the leading edge of the external clock CLK signal is aligned with the leading edge of the data signal applied to the D terminal, although the data signal has only a 25% duty cycle. It is common for the data signal to be synchronized to the clock CLK signal before being applied to the integrated circuit 10 because the clock CLK signal may have been used to clock the data out of another integrated circuit (now shown). Primarily because of the capacitive loading of the signal path 12, the delayed clock CLK-DEL signal coupled to the NAND gate 22 is delayed by one-quarter of a clock period, or 90.degree., as illustrated by the third waveform of the timing diagram. As a result, by the time the CLK-DEL signal has gone high, the data signal has gone low so that the output OUT signal remains high. Thus, because of the delay of the external clock, the external clock signal is ineffective in clocking the data through the NAND gate 22.
As clock speeds continue to increase, timing tolerances have become increasingly severe. This problem is exacerbated by the increasing complexity in contemporary integrated circuits which require a large number of events to be accurately timed with respect to each other. These timing constraints threaten to create a significant road block to increasing the operating speeds of many conventional integrated circuits.